CH7202 Datasheet, PDF (1/16 Pages) List of Unclassifed Manufacturers – MPEG to TV Encoder with 8-bit Input

CHRONTEL
CH7202
MPEG to TV Encoder with 8-bit Input
Features
• Outputs NTSC, PAL (B,D,G,H,I) and PAL-M (NTSC-
J or PAL-60 available as options)
• 8-bit YCrCb (4:2:2) input format
• Master or slave mode operation
• Triple 9-bit DAC for composite and S-video output
• 27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
• Low-jitter phase-locked loop circuitry operates using a
low-cost 14.31818 MHz crystal
• 40.5 or 33.9 MHz video decoder clock output
• 16.934 or 11.289 MHz audio decoder clock output
• 13.5 MHz and 27 MHz video pixel clock outputs
• Internal 4.6 MHz (m ax) luminance and 1.3 MHz
chrom inance filters
• Sub-carrier genlocked to HSYNC* and VSYNC*
• Sleep mode
• CMOS technology in 44-pin PLCC
• 5V single-supply operation
Description
The CH7202 vi deo encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTS C or PAL video signals, the CH7202 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7202 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7202 will accept HSYNC*,
VSYNC*, and 2XPCLK clock inputs during slave
mode operation. Timing signals from the PLLs can be
used to generate the horizontal and vertical sync signals
which enable operating the CH7202 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
MOD 0
MOD 1
FS
YCSWAP C bSWAP
VDD
AVDD
R SET
M/S*
YC[7 :0],
H SYNC*
VSYNC*
PCLK
2XPC LK
DCLK
AC LK
8
I NTE RFACE
BL AN KING
H ,V SYNC
GEN ERATO R
L INE AR
INTE RP OLATO R
S TAT E
M ACHI NE
1/ 2
PLL1
PLL2
OSC
M
Y
U
X
FILTER
U
FILTER
M
U
X
X
IR EF
DAC
Σ
DAC
Σ
DAC
V
FILTER
M
U
X
X
B LA NKIN G
COL O R-B URST
CO NT RO L
S IN + COSINE
GEN ER ATOR
201-0000-030 Rev 2.0, 6/2/99
XI XO/FIN
GN D
A GN D
Figure 1: Functional Block Diagram
Y
C VBS
C
1