CH7003B Datasheet, PDF (1/50 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
CH7003B
Digital PC to TV Encoder
Features
• Input data path handles 8, 12, or 16-bit words in
multiplexed or non-multiplexed form
• Decodes pixel data in YCrCb (CCIR601 or 656) or
RGB (15, 16 or 24-bit) formats
• Supports 640x480, 640x400, 720x400, 800x600 and
512x384 input resolutions
• Adjustable underscan for most modes† ¥
• High quality 4-line flicker filtering †
• High resolution on-chip PLL
• Fully programmable through I²C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• CCIR624-3 compliant (see exceptions)
• Auto-detection of TV presence
• Sub-carrier genlock and dot crawl control
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in a 44-pin PLCC, 44-pin TQFP
† Patent number 5,781,241
Â¥ Patent number 5,914,753
General Description
Chrontel’s CH7003 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format, with simultaneous composite
and S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 9-
bit DAC interface, and new adaptive flicker filter, and high
accuracy low-jitter phase locked loop to create outstanding
quality video. Through its TrueScale^TM scaling and de-
flickering engine, the CH7003 supports full vertical and
horizontal underscan capability and operates in 5 different
resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7003 ideal for system-level
PC solutions. All features are software programmable
through a standard I²C port, to enable a complete PC
solution using a TV as the primary display.
LINE
MEMORY
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING & DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
I²C REGISTER & CONTROL
BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC GENERATOR
SC SD ADDR
XCLK
H V XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
201-0000-023 Rev 4.1, 8/2/99
Y/R
C/G
CVBS/G
RSET
1