AZ10EL16VO Datasheet, PDF (1/18 Pages) List of Unclassifed Manufacturers – ECL/PECL Oscillator Gain Stage and Buffer with Enable

AZ10EL16VO
AZ100EL16VO
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage and Buffer with Enable
FEATURES
• Green and RoHS Compliant Available
• 250ps Propagation Delay on Q¯ Output
• High Voltage Gain vs. Standard EL16
• For Oscillator Applications
• Available in 2x2 or 3x3mm MLP Package
• 75kΩ Enable Pull-Down Resistor
• S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek Website
DESCRIPTION
The AZ10/100EL16VO is an oscillator gain stage with a high gain output buffer including an enable. The
Q_HG/Q¯ _HG outputs have a voltage gain several times greater than the Q/Q¯ outputs. An enable input (E¯N¯ ) allows
continuous oscillator operation. When E¯N¯ is LOW or floating (NC), input data is passed to both sets of outputs.
When E¯N¯ is HIGH, the Q_HG/Q¯ _HG outputs will be forced LOW/HIGH respectively, while input data will continue to
be passed to the Q/Q¯ outputs. The E¯N¯ input can be driven with an ECL/PECL signal or a CMOS logic signal.
The input impedance of the D/D¯ inputs remain constant for all operating modes since forcing the outputs via the
E¯N¯ pin does not power-down the chip but only disables the high gain Q_HG/Q¯ _HG outputs.
Input protection diodes are included on the D/D¯ inputs for enhanced ESD protection.
The EL16VO also provides a V_BB output that supports 1.5mA sink/source current. When used, the V_BB pin
should be bypassed to ground or V_CC via a 0.01μF capacitor.
Any used output must have an external pull down resistor. For 3.3V operation, an 180Ω resistor to V_EE is
recommended if an AC coupled load is present. At 5.0V, a 330Ω resistor is recommended for the AC load case.
Alternately, a 50Ω load terminated to V_CC – 2V or the Thevenin equivalent may be driven directly. Unused outputs
may be left floating (NC).
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN/PAD DESCRIPTION
Q
PIN
FUNCTION
Q
D/D¯
Data Inputs
Q/Q¯
Data Outputs
D
Q_HG Q_HG/Q¯ _HG Data Outputs w/High Gain
V_BB
Reference Voltage Output
D
Q_HG E¯N¯
Enable Input
V_CC
Positive Supply
EN
V_EE
Negative Supply
V_BB
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com