AZ10E111 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – 1:9 Differential Clock Driver

DATA SHEET
AZ10E111
ARIZONA MICROTEK, INC.
AZ100E111
1:9 Differential Clock Driver
FEATURES
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• Enable
• V_BB Output
• Extended 100E V_EE Range of -4.2V to -5.46V
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for Motorola MC10EL111 & MC100EL111
• Manufactured Under License By Lucent Technologies
PACKAGE AVAILABILITY
SUFFIX DESCRIPTION
FN Plastic 28 PLCC
DESCRIPTION
The AZ10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It
accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is
fanned-out to 9 identical differential outputs. An Enable input is also provided. A HIGH disables the device by
forcing all Q outputs LOW and all QN outputs HIGH.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent t_pd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated
into 50Ω , even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs
on the same package side (i.e. sharing the same V_CCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps)
of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
VEE
ENN
Q0
Q0N
25
24
26
27
Q1 VCCO Q1N
23
22
21
Q2
Q2N
20
19
18
17
Q3
Q3N
LOGIC SYMBOL
Q0
QON
IN
28
VCC
1
INN
2
Pinout: 28-Lead PLCC
(Top View)
16
Q4
15
VCCO
14
Q4N
Q1
Q1N
Q2
Q2N
VBB
3
NC
4
13
Q5
12
Q5N
5
6
7
8
9
10
11
IN
INN
ENN
Q3
Q3N
Q4
Q4N
Q8N
Q8
Q7N VCCO
Q7
Q6N
Q6
Q5
Q5N
PIN DESCRIPTION
Q6
PIN
FUNCTION
Q6N
IN, INN
Differential Input Pair
Q7
ENN
Enable
Q7N
Q0, Q0N-Q8N, Differential Outputs
Q8
Q8
VBB Output
VBB
Q8N
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