AZ100LVE310 Datasheet, PDF (1/5 Pages) List of Unclassifed Manufacturers – ECL/PECL 2:8 Differential Clock Driver

ARIZONA MICROTEK, INC.
AZ100LVE310
ECL/PECL 2:8 Differential Clock Driver
FEATURES
• Operating Range of 3.0V to 5.5V
• Low Skew
• Guaranteed Skew Spec
• Differential Design
• V_BB Output
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC100LVE310 & MC100E310
PACKAGE AVAILABILITY
PACKAGE
PART NO.
MARKING
PLCC 28
AZ100LVE310FN AZM100LVE310
PLCC 28 T&R AZ100LVE310FNR2 AZM100LVE310
DESCRIPTION
The AZ100LVE310 is a low skew 2:8 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE310 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE310 provides a V_BB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V_BB reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The V_BB pin should be used only
as a bias for the AZ100LVE310 as its current sink/source capability is limited. When used, the V_BB pin should be
bypassed to ground via a 0.01µF capacitor.
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same V_CCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
Q0
Q0
Q1
V_CCO
Q1
Q2
Q2
25
24
23
22
21
20
19
V_EE 26
18 Q3
CLK_SEL 27
17 Q3
CLKa 28
16 Q4
V_CC
1
CLKa
2
V_BB
3
Pinout: 28-Lead
PLCC (top view)
15 V_CCO
14 Q4
13 Q5
CLKb
4
5
6
CLKb NC
12 Q5
7
8
9
10
11
Q7
V_CCO
Q7
Q6
Q6
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • [phone] • FAX [phone]
www.azmicrotek.com