ADC-321 Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – 8-Bit, 50MHz Video A/D Converter

®
®
ADC-321
8-Bit, 50MHz
Video A/D Converter
FEATURES
• Low power dissipation (180mW max.)
• Input signal bandwith (100MHz)
• Optional synchronized clamp function
• Low input capacitance (15pF typ.)
• +5V or +5V/+3.3V power supply operation
• Differential nonlinearity (±½LSB max.)
• Optional self-biased reference
• CMOS/TTL compatible inputs
• Outputs 3-state TTL compatible
• Surface mount package
GENERAL DESCRIPTION
The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub-
ranging A/D converter. The ADC-321 achieves a sampling rate
comparable to flash converters by employing a sub-ranging
technique which uses multiple comparator blocks each
containing a sample-and-hold amplifier. The ADC-321 can
operate with either a single +5V or dual +5V and +3.3V power
source to allow easy interfacing with 3.3V logic.
An optional synchronous clamp function useful for video signal
processing is provided. The ADC-321 is well suited for the
portable video signal processors due to its low 125mW typical
power dissipation. The ADC-321 also features ±0.5 LSB max.
differential non-linearity, a self bias function that can eliminate the
need for external references, SNR with THD of 45dB, a small
32-pin QFP package and an operating temperature range
of –40 to +85°C
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
1 BIT 8 (LSB)
2 BIT 7
3 BIT 6
4 BIT 5
5 BIT 4
6 BIT 3
7 BIT 2
8 BIT 1 (MSB)
9 TEST
10 +DVS (Digital)
11 TEST
12 A/D CLOCK
13 NO CONNECTION
14 NO CONNECTION
15 CLAMP IN (CLP)
16 +AVS (Analog)
32 NO CONNECTION
31 DIGITAL GROUND (DGND)
30 OUTPUT ENABLE (OE)
29 CLAMP ENABLE (CLE)
28 DIGITAL GROUND (DGND)
27 CLAMP CONTROL (COP)
26 CLAMP REF. (VREF)
25 REF. BOTTOM SENSE (VRBS)
24 REF. BOTTOM (VRB)
23 ANALOG GROUND (AGND)
22 ANALOG GROUND (AGND)
21 ANALOG IN (VIN)
20 +AVS (Analog)
19 +AVS (Analog)
18 REF. TOP (VRT)
17 REF. TOP SENSE (VRTS)
+AVS 16
VRTS 17
VRT 18
+AVS 19
+AVS 20
VIN 21
AGND 22
AGND 23
VRB 24
VRBS 25
VREF 26
DGND 28
CLAMP CONTROL 27
CLAMP ENABLE 29
Reference
Supply
Clock
Generator
–
+
A
4-Bit
Lower
Sampling
Comparator
B
A
4-Bit
Lower
Encoder
B
Lower
Data
Latch
30 OUTPUT ENABLE
31 DGND
1 BIT 8 (LSB)
2 BIT 7
3 BIT 6
4 BIT 5
4-Bit
Upper
Sampling
Comparator
4-Bit
Upper
Encoder
D-FF
Upper
Data
Latch
5 BIT 4
6 BIT 3
7 BIT 2
8 BIT 1 (MSB)
12 A/D CLOCK
15 CLAMP IN
9 TEST (Open)
10 +DVS
11 TEST (Open)
Figure 1. ADC-321 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA.) • Tel: [phone] Fax: [phone] • Email: [e-mail] • Internet: www.datel.com