A3P030 Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC^®3 Flash Family FPGAs
with Optional Soft ARM^® Support
Product Brief
®
Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except A3P030 and ARM^®-
enabled ProASIC^®3 devices) via JTAG (IEEE 1532–
compliant)
• FlashLock^® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os (A3P030 only)
• Programmable Output Slew Rate (except A3P030) and
Drive Strength
• Weak Pull-Up/Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL (except A3P030)
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback, Multiply/Divide,
Delay Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• CoreMP7Sd (with debug) and CoreMP7S (without debug
SRAMs and FIFOs (except A3P030)
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Soft ARM7™ Core Support in M7 ProASIC3 Devices
• CoreMP7Sd (with debug) and CoreMP7S (without
debug)
Table 1 • ProASIC3 Product Family
ProASIC3 Devices
ARM^®-Enabled
ProASIC3 Devices¹
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP²
Integrated PLL in CCCs
VersaNet Globals³
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P030 A3P060 A3P125 A3P250
A3P400
A3P600
A3P1000
30 k
768
–
–
1k
–
–
6
2
81
QN132
VQ100
60 k
1,536
18
4
1k
Yes
1
18
2
96
QN132
VQ100
TQ144
FG144
125 k
3,072
36
8
1k
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
M7A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
M7A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
M7A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
235
M7A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
QN132⁵
VQ100
PQ208
FG144,
FG256⁵
PQ208
PQ208
PQ208
FG144, FG256, FG144, FG256, FG144, FG256,
FG484
FG484
FG484
Notes:
1. Refer to the CoreMP7 datasheet for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet.
5. The M7A3P250 device does not support this package.
May 2007
© 2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.