8051 Datasheet, PDF (1/3 Pages) List of Unclassifed Manufacturers – HDL model of the Intel™ 8-bit 8051 micro controller

April 11, 2006 (version 1.0)
ALDEC 8051 IP Core Data Sheet
Overview
Features
Pinout
The 8051 core is the HDL model of the Intel™ 8-bit 8051 micro controller. The model is fully
compatible with the Intel 8051 standard.
x Opcode and Cycle Equivalent to Intel standard 8051
x Support for Intel Hex file format
x Up to 4K Bytes Internal Program Memory (ROM)
x Up to 128 Bytes Internal Data Memory (RAM)
x Up to 64K Bytes External Program Memory address space
x Up to 64K Bytes External Data Memory address space
x Up to 128 Special Function Registers (SFR)
x 32 bi-directional and individually addressable I/O Lines
x Two 16-bit timer/counters
x Full Duplex UART (Serial Port)
x 6-Source/5-Vector Interrupt Structure with Two Priority Levels
Table 1: Core Signal Pinout
Name
CLK ¹⁾
Direction
Input
EA ²⁾
Input
RST ²⁾
Input
ALE ²⁾
Output
PSEN ²⁾
Output
P0[7:0] ³⁾
Bidirectional
P1[7:0] ³⁾
Bidirectional
P2[7:0] ³⁾
Bidirectional
P3[7:0] ³⁾
Bidirectional
Polarity
-
Low
High
High
Low
-
-
-
-
Clock input
Description
External Access
Synchronous reset
Address Latch Enable
Program Store Enable
Port P0
Port P1
Port P2
Port P3
Notes:
1) XTAL1 and XTAL2 original device pins were replaced with one CLK (clock) input
signal. The clock frequency value has no limitations during the functional simulation.
2) EA, RST, ALE and PSEN signals behave exactly the same as the original device and
are compatible with the Intel 8051 standard.
3) In the synthesizable model, each bidirectional pin is defined in the core interface as
two separated VHDL ports. Optionally, using the Aldec VHDL/Verilog Interface, it can
be merged to one bidirectional VHDL port. The behavioral model has bidirectional
ports.
www.aldec.com
©2006 Aldec, Inc. All rights reserved