NE555 Datasheet, PDF (1/3 Pages) NXP Semiconductors – Timer

NE555
Description
These devices are monolithic timing circuits capable of producing accurate time delays or oscillation.
Inthe time delay mode of operation, the timed interval is controll ed by a single external resistor and capacit
or netw ork. In the astable mode of operation, the frequency and duty cy cle may be independently
controlled wi th two external resistors and a si ngle external capacitor.
Features
• Timing from Microseconds to Hours
• Astable or Monostable Operation
• Adjustable Duty Cycle
• TTL - Compatible Output Can Sink or Source Up to 200 mA
• _{Temperature Stability of 0.005% per} o_C
• Direct Replacement for Signetics NE555 Timer
Applications
• Precision timing
• Pulse generation
• Sequential timing
• Time delay generation
• Pulse w idth modulation
• Pulse position modulation
• Missing pulse detector
Pin Configuration
TOP VIEW
DIP-8
SOP-8
P ack age
Internal Block Digram
RESET can override TRIGGER, which can override THRESHOLD
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