M12L16161A-2Q Datasheet, PDF (9/28 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
M12L16161A (2Q)
Operation Temperature Condition -40°C~85°C
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn _{CS RAS CAS WE} DQM BA A10/AP A9~A0 Note
Register
Mode Register Set
H
XLL
L
L
X
OP CODE
1,2
Refresh
Auto Refresh
Entry
Self Refresh
Exit
H
H
LL
L
H
X
L
L
H
L
H
H
H
X
HX
X
X
3
X
3
X
3
3
Bank Active & Row Addr.
H
XLL
H
H
X V Row Address
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
L ^Column 4
XLH
L
H
XV
Address
H _(A0~A7) 4,5
Write & Column
Address
Auto Precharge Disable
Auto Precharge Enable
H
L ^Column 4
XLH
L
L
XV
Address
H _(A0~A7) 4,5
Burst Stop
H
XLH
H
L
X
X
6
Precharge
Bank Selection
Both Banks
H
XLL
H
L
XV
L
X
4
XH
4
Clock Suspend or
Entry
H
L
H
X
X
X
X
Active Power Down Mode
LH
H
H
X
Exit
L
HXX
X
X
X
Entry
H
L
H
X
X
X
X
LH
H
H
Precharge Power Down Mode
X
Exit
L
H
H
X
X
X
X
LH
H
H
DQM
H
X
V
X
7
No Operation Command
H
X
H
X
X
X
X
X
H
LH
H
H
(V= Valid, X= Don’t Care, H= Logic High, L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks idle state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2012
Revision : 1.0
9/28