F25L02PA Datasheet, PDF (9/35 Pages) Elite Semiconductor Memory Technology Inc. – Single supply voltage 2.7~3.6V

ESMT
F25L02PA
„ INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L02PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
significant bit. CE must be driven low before an instruction is
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Operation
Read
Fast Read
Fast Read Dual
Output^11,12
Sector Erase⁴ (4K Byte)
Block Erase^4, (64K Byte)
Chip Erase
Page Program (PP)
Read Status Register
(RDSR) ⁶
Write Status Register
(WRSR)
Write Enable (WREN) ⁹
Write Disable (WRDI)
Deep Power Down (DP)
Release from Deep
Power Down (RDP)
Read Electronic
Signature (RES) ⁷
Jedec Read ID
(JEDEC-ID) ⁸
Read ID (RDID) ¹⁰
Max.
Freq
1
S_IN S_OUT
33 MHz 03H Hi-Z
0BH Hi-Z
2
S_IN
A₂₃-A₁₆
A₂₃-A₁₆
S_OUT
Hi-Z
Hi-Z
3
S_IN S_OUT
A₁₅-A₈ Hi-Z
A₁₅-A₈ Hi-Z
Bus Cycle ^1~3
4
S_IN S_OUT S_IN
A₇-A₀ Hi-Z X
A₇-A₀ Hi-Z X
5
S_OUT
D_OUT0
X
3BH
A₂₃-A₁₆
A₁₅-A₈
A₇-A₀
X
20H Hi-Z A₂₃-A₁₆ Hi-Z A₁₅-A₈ Hi-Z A₇-A₀ Hi-Z -
-
D8H Hi-Z A₂₃-A₁₆ Hi-Z A₁₅-A₈ Hi-Z A₇-A₀ Hi-Z -
-
60H /
C7H
Hi-Z
-
-
-
-
-
-
-
-
02H Hi-Z A₂₃-A₁₆ Hi-Z A₁₅-A₈ Hi-Z A₇-A₀ Hi-Z D_IN0 Hi-Z
50MHz
05H Hi-Z X D_OUT -
-
-
-
-
-
~
01H Hi-Z D_IN Hi-Z -
-
-.
-
-
-
06H Hi-Z -
-
-
-
-
-
-
-
100MHz _{04H Hi-Z -}
-
-
-
-
-
-
-
B9h Hi-Z -
-
-
-
-
-
-
-
ABH Hi-Z -
-
-
-
-
-
-
-
ABH Hi-Z X
X X X X X X 11H
9FH Hi-Z X 8CH X 30H X 12H -
90H Hi-Z
00H
Hi-Z
00H
Hi-Z
00H
01H
Hi-Z
Hi-Z
X
X
-
8CH
11H
6
S_IN S_OUT
X D_OUT1
X
D_OUT0
N
S_IN S_OUT
X cont.
X cont.
D_OUT0~1
cont.
-
-
-
-
-
-
-
-
-
-
-
-
Up to
D_IN1 Hi-Z 256 Hi-Z
bytes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X 11H -
-
X 8CH -
-
Note:
1.
2.
3.
4.
5.
Operation: S_IN = Serial In, S_OUT = Serial Out, Bus Cycle 1 = Op Code
X = Dummy Input Cycles (V_IL or V_IH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One bus cycle is eight clock periods.
Sector Earse addresses: use A_MS -A₁₂, remaining addresses can be V_IL or V_IH
Block Earse addresses: use A_MS -A₁₆, remaining addresses can be V_IL or V_IH
To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 30H as memory type; third byte 12H as
memory capacity.
9. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.2
9/35