F25D08QA_1 Datasheet, PDF (9/69 Pages) Elite Semiconductor Memory Technology Inc. – Fast Read for SPI mode

ESMT
F25D08QA
Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles,
address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enable.
CE
MODE3
SCK MODE0
0 12 3 45 67
SI
35
MSB
SO
HIGH IMPEDANCE
Quad Peripheral Interface (QPI) operation
To use QPI protocol, the host drives CE low then sends the Fast Read command, 0BH, followed by 6 address cycles and 4 dummy
cycles. Most significant bit (MSB) comes first (Please refer to Figure 8-2).
After the dummy cycle, the Quad Peripheral Interface (QPI) Flash Memory outputs data on the falling edge of the SCK signal starting
from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high
transition on CE . The internal address pointer automatically increases until the highest memory address is reached. When reached the
highest memory address, the address pointer returns to the beginning of the address space.
Reset QPI mode
By issuing F5H command, the device is reset to 1-I/O SPI mode.
CE
MODE3
01
SCK MODE0
SIO3~ SIO0
F5
Fast Read Quad I/O mode (4READ)
To increase the code transmission speed, the device provides a "Fast Read Quad I/O Mode" (4READ). By issuing command code EBH,
the 4READ mode is enabled. The number of dummy cycle increase from 4 to 6 cycles. The read cycle frequency will increase from
84MHz to 104MHz. (Please refer to Figure 10-2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2013
Revision: 1.1
9/69