M24L816512DA Datasheet, PDF (8/12 Pages) Elite Semiconductor Memory Technology Inc. – 8-Mbit (512K x 16) Pseudo Static RAM

ESMT
M24L816512DA
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during
15μs shown as in Avoidable timing 1 or toggle CE1 to high (≧t_RC) one time at least shown as in Avoidable Timing 2.
Abnormal Timing
CE1
≧15μs
WE
Address
＜ tRC
Avoidable Timing 1
≧15μs
CE1
WE
Address
Avoidable Timing 2
CE1
WE
Address
≧ tRC
＜ tRC
≧15μs
≧ tRC
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
8/12