M12S16161A_1 Datasheet, PDF (7/30 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Operation Temperature Condition -40°C~85°C
Mode Register
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0001
JEDEC Standard Test Set (refresh counter test)
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
x x 1 0 0 LTMODE
WT
BL
Burst Read and Single Write (for Write
Through Cache)
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
Use in future
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
x x x 1 1 v v v v v v v Vender Specific
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
v =Valid
0 0000
LTMODE WT
BL
Mode Register Set
x =Don’t care
Burst length
Bit2-0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Wrap type
0
Sequential
1
Interleave
Mode Register Write Timing
Latency mode
Bits6-4
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A10, BA
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2007
Revision : 1.0
7/30