M24D816512DA Datasheet, PDF (6/13 Pages) Elite Semiconductor Memory Technology Inc. – 8-Mbit (512K x 16) Pseudo Static RAM

ESMT
AC Test Loads and Waveforms
M24D816512DA
Parameters
R1
R2
R_TH
V_TH
1.8V (V_CC)
14000
14000
7000
0.90
Switching Characteristics Over the Operating Range [9, 10, 11, 12]
Parameter
Read Cycle
t_RC[14]
t_CD [15]
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_DBE
t_LZBE
t_HZBE
Description
Read Cycle Time
Chip Deselect Time CE1 = HIGH orCE2 = LOW,
BLE / BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[10, 11, 13]
OE HIGH to High Z[10, 11, 13]
CE1 LOW and CE2 HIGH to Low Z[10, 11, 13]
CE1 HIGH or CE2 LOW to High Z[10, 11, 13]
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[10, 11, 13]
BLE / BHE HIGH to Low Z[10, 11, 13]
-55
Min.
Max.
55
80000
5
55
5
55
25
5
20
10
20
55
5
20
Unit
Ω
Ω
Ω
V
-70
Min. Max.
Unit
70
80000 ns
ns
5
70
ns
5
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
70
ns
5
ns
25
ns
Notes:
9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels
of V_CC(typ.)/2, input pulse levels of 0V to V_CC, and output loading of the specified I_OL/I_OH as shown in the “AC Test Loads and
Waveforms” section.
10.At any given temperature and voltage conditions t_HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t_HZOE is less than t_LZOE, and
t_HZWE is less than t_LZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V)
11.t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high-impedance state.
12.The internal Write time of the memory is defined by the overlap of WE , CE1 = V_IL and CE2 = V_IH, BHE and/or BLE = V_IL.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input
set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13.High-Z and Low-Z parameters are characterized and are not 100% tested.
14.If invalid address signals shorter than min. t_RC are continuously repeated for 80 µs, the device needs a normal read timing (t_RC)
or needs to enter standby state at least once in every 80 µs.
15.Whenever CE1 = HIGH or CE2 = LOW, BHE / BLE are taken inactive, they must remain inactive for a minimum of 5 ns.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
6/13