M24D16161DA Datasheet, PDF (6/12 Pages) Elite Semiconductor Memory Technology Inc. – 16-Mbit (1M x 16) Pseudo Static RAM

ESMT
M24D16161DA
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14] (continued)
Parameter
Write Cycle[15]
t_WC
t_SCE
t_AW
t_CD
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Description
Write Cycle Time
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Chip Deselect Time CE1= HIGH or CE2 = LOW,
BLE / BHE High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z[10, 11, 12]
WE HIGH to Low-Z[10, 11, 12]
-70
Min.
Max.
70
40000
60
60
15
0
0
50
60
25
0
25
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE , CE1 = V_IL or CE2 = V_IH, BHE and/or BLE = V_IL.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data
input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
6/12