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M12L128324A Datasheet, PDF (6/47 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM | |||
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ESMT
CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHZ)
Parameter
Symbol
Min
Input capacitance (A0 ~ A10, BA0 ~ BA1)
CIN1
2
Input capacitance
CIN2
2
(CLK, CKE, CS , RAS , CAS , WE & DQM)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
M12L128324A
Max
Unit
4
pF
4
pF
5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise notedï¼TA = 0 to 70 °C
Parameter
Symbol
Test Condition
CAS
Latency
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
Burst Length = 1
tRC ⥠tRC(min)
IOL = 0 mA
CKE ⤠VIL(max), tcc = 10ns
CKE & CLK ⤠VIL(max), tcc = â
CKE ⥠VIH(min), CS ⥠VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE ⥠VIH(min), CLK ⤠VIL(max), tcc = â
input signals are stable
CKE ⤠VIL(max), tcc = 10ns
CKE & CLK ⤠VIL(max), tcc = â
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
ICC3NS
CKE ⥠VIH(min), CS ⥠VIH(min), tcc = 15ns
Input signals are changed one time during 30ns
CKE ⥠VIH(min), CLK ⤠VIL(max), tcc = â
input signals are stable
Operating Current
ICC4
(Burst Mode)
Refresh Current
ICC5
Self Refresh Current
ICC6
IOL = 0 mA
Page Burst
2 Banks activated
tCK = tCK(min)
tRC ⥠tRC(min)
CKE ⤠0.2V
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Version
-6
-7
Unit Note
120 100 mA 1,2
2
mA
1
25
mA
9
7
mA
6
30
mA
15
mA
270 240 mA 1,2
270 240 mA
2
mA
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision: 1.2
6/47
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