M13S64164A_1 Datasheet, PDF (5/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DC Specifications
M13S64164A
Operation Temperature Condition -40°C~85°C
Parameter
Symbol
Test Condition
Operation Current
(One Bank Active)
IDD0
Operation Current
(One Bank Active)
IDD1
Precharge Power-down Standby
Current
IDD2P
t_RC = t_RC (min) t_CK = t_CK (min)
Active – Precharge
Burst Length = 2 t_RC = t_RC (min), CL=
2.5 I_OUT = 0mA, Active-Read-
Precharge
CKE ≤ V_IL(max), t_CK = t_CK (min), All
banks idle
Idle Standby Current
IDD2N ^{CKE ≥ VIH(min), CS ≥ VIH(min), tCK =}
t_CK (min)
Active Power-down
Current
Standby _IDD3P
All banks ACT, CKE ≤ V_IL(max), t_CK =
t_CK (min)
Active Standby Current
IDD3N
One bank; Active-Precharge, t_RC =
t_RAS(max), t_CK = t_CK (min)
Operation Current (Read)
IDD4R
Burst Length = 2, CL= 2.5 , t_CK = t_CK
(min), I_OUT = 0mA
Operation Current (Write)
IDD4W
Burst Length = 2, CL= 2.5 , t_CK = t_CK
(min)
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
t_RC ≥ t_RFC(min)
CKE ≤ 0.2V
Operation Current
(4 bank interleaving)
IDD7
Burst Length = 4, t_RC = t_RC (min),
I_OUT = 0mA
Note 1. Enable on-chip refresh and address counters.
Version
-5
-6
150
130
160
140
40
40
100
100
50
40
110
100
220
200
220
200
250
220
5
5
280
260
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA 1
mA
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
V_IH(AC) V_REF + 0.31
V
V_IL(AC)
V_REF - 0.31
V
V_ID(AC)
0.7
V_DDQ+0.6
V
Input Crossing Point Voltage, CLK and CLK inputs
V_IX(AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
Note
1
2
Note1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V_DD = 2.3V~2.7V, V_DDQ=2.3V~2.7V, T_A = 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Symbol
C_IN1
C_IN2
C_OUT
C_IN3
Min
Max
Unit
2.5
3.5
pF
2.5
3.5
pF
4.0
5.5
pF
4.0
5.5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.0
5/49