M12S64322A_09 Datasheet, PDF (5/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
CAPACITANCE (VDD = 2.5V, TA = 25 °C , f = 1MHZ)
Parameter
Symbol
Min
Input capacitance (A0 ~ A10, BA0 ~ BA1)
CIN1
2.5
Input capacitance
CIN2
2.5
(CLK, CKE, CS , RAS , CAS , WE & DQM)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
M12S64322A
Max
Unit
4
pF
4
pF
6.5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
Parameter
Symbol
Test Condition
CAS
Latency
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
Burst Length = 1
tRC ≥ tRC(min)
IOL = 0 mA
CKE ≤ VIL(max), tcc = 15ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
CKE ≤ VIL(max), tcc = 15ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 2clks
All other pins ≥ V_DD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
I_OL = 0 mA
3
Page Burst
2 Banks activated
2
Refresh Current
Self Refresh Current
ICC5
tRC ≥ tRC(min)
ICC6
CKE ≤ 0.2V
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Version
-6
-7
Unit Note
100 80 ^{mA 1,2}
1.5
mA
1.5
20
mA
10
10
mA
10
30
mA
10
mA
200 180
mA 1,2
180 160
200 180 mA
2
mA
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.1
5/46