M12L128324A-2E Datasheet, PDF (5/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870 _Ω
3.3V
1200 _Ω
VOH (DC) =2.4V , IOH = -2 mA
30pF
VOL (DC) =0.4V , IOL = 2 mA
Output
M12L128324A (2E)
Z0 =50 _Ω
Unit
V
V
ns
V
Vtt = 1.4V
50 _Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-5
-6
-7
Row active to row active delay
tRRD (min)
10
12
14
RAS to CAS delay
tRCD (min)
15
18
21
Row precharge time
tRP (min)
15
18
21
Row active time
tRAS (min)
40
42
42
tRAS (max)
100
@ Operating
tRC (min)
60
60
63
Row cycle time
@ Auto Refresh tRFC (min)
60
60
63
Last data in to col. address delay
tCDL (min)
1
Last data in to row precharge
tRDL (min)
2
Last data in to burst stop
tBDL (min)
1
Col. address to col. address delay t_CCD(min)
1
Number of valid
CAS latency = 3
2
Output data
CAS latency = 2
1
Unit
Note
ns
1
ns
1
ns
1
ns
1
us
1
ns
1, 5
CLK
2
CLK
2
CLK
2
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t_RFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2012
Revision: 1.0
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