F25S004A Datasheet, PDF (5/33 Pages) Elite Semiconductor Memory Technology Inc. – 2.5V Only 4 Mbit Serial Flash Memory

ESMT
F25S004A
Table2 : F25S004A Block Protection Table
Protection Level
0
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
Status Register Bit
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protected Memory Area
Block Range
Address Range
None
None
Block 7
70000H – 7FFFFH
Block 6~7
60000H – 7FFFFH
Block 4~7
40000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~7
00000H – 7FFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as WP is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP pin driven low (V_IL), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (V_IH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.1
5/33