M52S128168A-2E Datasheet, PDF (40/47 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
M52S128168A (2E)
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined
by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.0
40/47