F50L512M41A Datasheet, PDF (23/36 Pages) Elite Semiconductor Memory Technology Inc. – SPI-NAND Flash Memory

ESMT
F50L512M41A
Program Operations and Serial Input
Page Program
The command sequence is follows:
„ 06h (WRITE ENABLE)
„ 02h (PROGRAM LOAD x1) / 32h (x4)
„ 10h (PROGRAM EXECUTE)
„ 0Fh (GET FEATURE command to read the status)
The page program operation sequence programs 1 byte to 2112 bytes of data within a page. If WRITE ENABLE command is not
issued (WEL bit is not set), then the rest of the program sequence is ignored. PROGRAM LOAD command requires 16-bit address with
4 dummy and a 12-bit column address, then the data bytes to be loaded into cache register. Only four partial page programs are
allowed on a single page. If more than 2112 bytes are loaded, then those additional bytes are ignored by the cache register.
After the data is loaded, PROGRAM EXECUTE command must be issued to transfer the data from cache register to main array, and is
busy for t_PROG time. PROGRAM EXECUTE command requires 24-bit address with 9 dummy bits and a 15-bit row address.
PROGRAM LOAD (02h) Timing
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
23/36