M53D128168A Datasheet, PDF (18/47 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Mobile DDR SDRAM

ESMT
Preliminary
M53D128168A
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
CLK
CL K
COMMAND
NOP
1
2
1tCK
WR IT E A WR IT E B
3
NOP
4
NO P
5
6
7
8
NOP
NO P
NOP
NOP
DQS
DQ's
D in A0 D in A1 Di n B0 D in B 1 Di n B2 D in B3
tCCD
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2008
Revision : 1.4
18/47