M12L16161A_1 Datasheet, PDF (18/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12L16161A
Operation temperature condition -40℃~85℃
Read & Write Cycle at Different Bank @ Burst Length = 4
CLOCK
CKE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14 ₁₅
16
17 ¹⁸
19
tRRD
HIGH
RAS
CAS
ADDR
BA
A10/AP
CL=2
DQ
CL=3
RAa
RAa
CAa
RBb
CBb RAc
CAc
RBb
QAa0 QAa1 QAa2 QAa3
RAc
*Note 1
tCDL
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
*Note: 1.tCDL should be met to complete write.
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
18/29