M53S64322A-2E Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – Bi-directional data strobe (DQS)

ESMT
Mobile DDR SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data
access per clock cycle
z Bi-directional data strobe (DQS)
z No DLL; CLK to DQS is not synchronized.
z Differential clock inputs (CLK and CLK )
z Four bank operation
z CAS Latency : 2, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8, 16
z Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
M53S64322A (2E)
512K x 32 Bit x 4 Banks
Mobile DDR SDRAM
z All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
z DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
z Data mask (DM) for write masking only
z V_DD/V_DDQ = 2.5V ± 0.2V
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z LVCMOS-compatible inputs
Ordering Information
Product ID
M53S64322A -5BG2E
M53S64322A -6BG2E
M53S64322A -7.5BG2E
Max Freq.
200MHz
166MHz
133MHz
V_DD
Package
Comments
2.5V 144 ball FBGA Pb-free
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DQS
DM
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
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