M52S128324A Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
SDRAM
FEATURES
y JEDEC standard 2.5V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature compensated Self Refresh)
Issued by EMRS
- DS (Driver Strength)
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
M52S128324A
1M x 32 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
Product No.
M52S128324A-7TG
MAX
FREQ.
143MHz
PACKAGE COMMENTS
86 TSOPII Pb-free
M52S128324A-7BG 143MHz 90 FBGA Pb-free
M52S128324A-10TG 100MHz 86 TSOPII Pb-free
M52S128324A-10BG 100MHz 90 FBGA Pb-free
GENERAL DESCRIPTION
The M52S128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
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