M52D2561616A-2F Datasheet, PDF (1/46 Pages) Elite Semiconductor Memory Technology Inc. – LVCMOS compatible with multiplexed address

ESMT
Mobile SDRAM
FEATURES
 1.8V power supply
 LVCMOS compatible with multiplexed address
 Four banks operation
 MRS cycle with address key programs
- CAS Latency (3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
 EMRS cycle with address
 All inputs are sampled at the positive going edge of the
system clock
 Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
 DQM for masking
 Auto & self refresh
 64ms refresh period (8K cycle)
M52D2561616A (2F)
Operation Temperature Condition -40°C~85°C
4M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M52D2561616A-5BIG2F 200MHz 54 Ball FBGA Pb-free
M52D2561616A-6BIG2F 166MHz 54 Ball FBGA Pb-free
M52D2561616A-7BIG2F 143MHz 54 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M52D2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16
bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
A
VSS DQ15 VSSQ
VDDQ DQ0 VDD
B
DQ14 DQ13 VDDQ
VSSQ DQ2 DQ1
C
DQ12 DQ11 VSSQ
VDDQ DQ4 DQ3
D
DQ10 DQ9 VDDQ
VSSQ DQ6 _DQ5
E
DQ8 NC
VSS
VDD LDQM DQ7
F
UDQM CLK CKE
G
A12 _A11
A9
CAS
RAS
WE
BA0 BA1
CS
H
A8
A7
A6
J
VSS A5
A4
A0
A1
A10
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 1.1
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