M24L28256DA Datasheet, PDF (1/10 Pages) Elite Semiconductor Memory Technology Inc. – 2-Mbit (256K x 8) Pseudo Static RAM

ESMT
M24L28256DA
PSRAM
2-Mbit (256K x 8)
Features
•Advanced low-power architecture
•High speed: 55 ns, 70 ns
•Wide voltage range: 2.7V to 3.3V
•Typical active current: 1 mA @ f = 1 MHz
•Low standby power
•Automatic power-down when deselected
Functional Description
The M24L28256DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable( CE ₁) and active HIGH Chip Enable ( CE ₂),and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by asserting Chip Enable One ( CE ₁) and Write
Pseudo Static RAM
Enable ( WE ) inputs LOW and Chip Enable Two ( CE ₂) input
HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is then
written into the location specified on the address pins (A₀
through A₁₇).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE ₁) and Output Enable ( OE ) inputs
LOW while forcing Write Enable ( WE ) HIGH. And Chip
Enable Two ( CE ₂) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected ( CE ₁
HIGH or CE₂ LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE ₁ LOW, CE₂ HIGH, and WE
LOW). See the Truth Table for a complete description of read
and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
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