M12L64164A Datasheet, PDF (1/44 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
SDRAM
M12L64164A
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6 μ s refresh interval
GENERAL DESCRIPTION
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
M12L64164A-5TG 200MHz TSOP II Pb-free
M12L64164A-6TG 166MHz TSOP II Pb-free
M12L64164A-7TG 143MHz TSOP II Pb-free
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ 5 10
DQ 6 11
V S S Q 12
DQ 7 13
VDD 14
L DQ M 15
W E 16
C AS 17
R AS 18
CS 19
A13 20
A12 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 27
54 VSS
53 DQ15
52 VS SQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VS SQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
39 U D Q M
38 CLK
37 CKE
36 N C
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
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