M12L128324A2E Datasheet, PDF (1/44 Pages) Elite Semiconductor Memory Technology Inc. – JEDEC standard 3.3V power supply

ESMT
SDRAM
(Preliminary)
M12L128324A (2E)
1M x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
y JEDEC standard 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
y All inputs are sampled at the positive going edge of the
system clock
y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)
ORDERING INFORMATION
Product ID
M12L128324A-5BG2E
M12L128324A-6BG2E
M12L128324A-7BG2E
Max
Freq.
200MHz
Package
90 FBGA
Comments
Pb-free
166MHz 90 FBGA Pb-free
143MHz 90 FBGA Pb-free
GENERAL DESCRIPTION
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1.4mm Body, 0.8mm Ball Pitch)
1
2
3 456
7
8
9
A DQ26 DQ24 VSS
VDD DQ23 DQ21
B DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5 A6
A10/AP A0 A1
H A7 A8 NC
NC BA1 A11
J CLK CKE A9
BA0 CS RAS
K DQM1 NC NC
CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
M VSSQ DQ10 DQ9
DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14
DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
R DQ13 DQ15 VSS
VDD DQ0 DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
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