F59L512M81A Datasheet, PDF (1/40 Pages) Elite Semiconductor Memory Technology Inc. – Command/Address/Data Multiplexed I/O Port

ESMT
Flash
FEATURES
 Voltage Supply: 2.7V ~ 3.6V
 Organization
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
 Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
 Page Read Operation
- Page Size: (2K + 64) Byte
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
 Memory Cell: 1bit/Memory Cell
 Fast Write Cycle Time
- Program time: 250us (Typ.)
- Block Erase time: 2ms (Typ.)
 Command/Address/Data Multiplexed I/O Port
 Hardware Data Protection
- Program/Erase Lockout During Power Transitions
 Reliable CMOS Floating Gate Technology
- ECC Requirement: 4 bit/512 Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
F59L512M81A
512Mbit (64M x 8)
3.3V NAND Flash Memory
 Command Register Operation
 Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
 NOP: 4 cycles
 Cache Program Operation for High Performance Program
 Cache Read Operation
 Copy-Back Operation
 EDO mode
 OTP Operation
 Bad-Block-Protect
ORDERING INFORMATION
Product ID
F59L512M81A -25TG
Speed
25 ns
Package
48 pin TSOPI
Comments
Pb-free
GENERAL DESCRIPTION
The device is a 64Mx8bit with spare 2Mx8bit capacity. The
device is offered in 3.3V V_CC Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 512 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2,112-Byte page in
typical 300us and an erase operation can be performed in typical
3ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Byte. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.0
1/40