F49L400UA Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory

EFST
F49L400UA/F49L400BA
4 Mbit (512K x 8/256K x 16)
3V Only CMOS Flash Memory
1. FEATURES
z Single supply voltage 3.0V-3.6V
z Fast access time: 70/90 ns
z 524,288 x 8 / 262,144 x 16 switchable by BYTE pin
z Compatible with JEDEC standard
- Pin-out, packages and software commands
compatible with single-power supply Flash
z Low power consumption
- 7mA typical active current
- 25uA typical standby current 
z 100,000 program/erase cycles typically
z Command register architecture
- Byte programming (9us typical)
- Sector Erase(sector structure: one 16 KB, two 8 KB,
one 32 KB, and seven 64 KB) 
z Auto Erase (chip & sector) and Auto Program
- Any combination of sectors can be erased
concurrently; Chip erase also provided.
- Automatically program and verify data at specified
address
z Erase Suspend/Erase Resume
- Suspend or Resume erasing sectors to allow the
read/program in another sector
z Ready/Busy (RY/ BY )
- RY/BY output pin for detection of program or erase
operation completion
z End of program or erase detection
- Data polling
- Toggle bits
z Hardware reset
- Hardware pin(_RESET ) resets the internal state machine
to the read mode
z Sector Protection /Unprotection
- Hardware Protect/Unprotect any combination of sectors
from a program or erase operation.
z Low V_CC Write inhibit is equal to or less than 2.0V
z Boot Sector Architecture
- U = Upper Boot Sector
- B = Bottom Boot Sector
z Packages available:
- 48-pin TSOPI
2. ORDERING INFORMATION
Part No
F49L400UA-70T
F49L400BA-70T
Boot
Upper
Bottom
Speed
70 ns
70 ns
Package
TSOPI
TSOPI
Part No
F49L400UA-90T
F49L400BA-90T
Boot
Upper
Bottom
Speed
90 ns
90 ns
Package
TSOPI
TSOPI
3. GENERAL DESCRIPTION
The F49L400UA/F49L400BA is a 4 Megabit, 3V only
CMOS Flash memory device organized as 512K bytes of
8 bits or 256K words of 16bits. This device is packaged in
standard 48-pin TSOP. It is designed to be programmed
and erased both in system and can in standard EPROM
programmers.
With access times of 70 ns and 90 ns, the
F49L400UA/F49L400BA allows the operation of
high-speed microprocessors. The device has separate
chip enable _CE , write enable WE , and output enable
OE ^{controls. EFST's memory devices reliably store}
memory data even after 100,000 program and erase
cycles.
The F49L400UA/F49L400BA is entirely pin and
command set compatible with the JEDEC standard for 4
Megabit Flash memory devices. Commands are written to
the command register using standard microprocessor
write timings.
The F49L400UA/F49L400BA features a sector erase
architecture. The device memory array is divided into one
16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64
Kbytes. Sectors can be erased individually or in groups
without affecting the data in other sectors. Multiple-sector
erase and whole chip erase capabilities provide the
flexibility to revise the data in the device.
The sector protect/unprotect feature disables both
program and erase operations in any combination of the
sectors of the memory. This can be achieved in-system or
via programming equipment.
A low V_CC detector inhibits write operations on loss of
power. End of program or erase is detected by the
Ready/Busy status pin, Data Polling of DQ7, or by the
Toggle Bit I feature on DQ6. Once the program or erase
cycle has been successfully completed, the device
internally resets to the Read mode.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1
1/47