PBL3766 Datasheet, PDF (17/18 Pages) Ericsson – Subscriber Line Interface Circuit

PBL 3766
Enable Input (E0)
dissipators, when transients are clamped Power-up Sequence
TTL compatible enable input E0 controls
the function of the DET output.
E0, when set to logic level low, enables
the DET output, which is a collector output
with internal pull-up resistor (approx.
15 kohms) to V_CC. A DET output at logic
level low indicates triggered detector
condition (loop current above threshold
current or telephone off-hook during
ringing). A DET output at logic level high
indicates a non triggered detector
condition.
E0, when set to logic level high disables
the DET output; i.e. it appears as a resist-
or connected to V_CC.
Table 2 summarizes the above descrip-
tion of the enable input.
Overvoltage Protection
The PBL 3766 SLIC must be protected
and of being fuses, when the line is
exposed to a power cross. Ericsson
Components AB offers a series of thick
film resistors networks (e g PBR 51-series
and PBR 53-series) designed for this
application.
Also devices with a build in resetable
fuse function is offered (e g PBR 52-
series) including positive temperature
coefficient (PTC) resistors, working as
resetable fuses, in series with thick film
resistors. Note that it is important to
always use PTC's in series with resistors
not sensitive to temperature, as the PTC
will act as a capacitance for fast
transients and therefore the ability to
protect the SLIC will be reduced.
If there is a risk for overvoltages on the
V_Bat terminal on the SLIC, then this
terminal should also be protected.
The voltage at pin VBAT sets the sub-
strate voltage, which must at all times be
kept more negative than the voltage at
any other terminal. This is to maintain
correct junction isolation between devices
on the chip. To prevent possible latch-up,
the correct power-up sequence is to
connect ground and V_Bat, then other
supply voltages and signal leads. Should
the V_Bat supply voltage be absent, a diode
with a 2 A current rating, connected with
its cathode to V_EE and anode to V_Bat,
ensures the presence of the most
negative supply voltage at the VBAT
terminals.
The V voltage should not be applied
Bat
at a faster rate than ∂V_Bat/∂t = 4 V/µsec or
with a time constant formed by a 5.1 ohm
resistor in series with the VBAT pin and a
0.47 microfarad capacitor from the VBAT
against overvoltages and power crosses.
Refer to Maximum Ratings, TIPX and
RINGX terminals for maximum allowable
continuous and transient voltages, that
may be applied to the SLIC. The circuit
shown in figure 11 utilizes series resistors
(R_F, R_F) together with a programmable
overvoltage protector (e g Texas Instru-
ment TISP PBL1), serving as a secondary
protection.
The protection network in figure 11 is
designed to meet requirements in CCITT
K20, Table 1. The TISP PBL1 is a dual
forward-conducting buffered p-gate
overvoltage protector. The protector gate
references the protection (clamping)
voltage to negative supply voltage (i e the
battery voltage, V_Bat). As the protection
voltage will track the negative supply
voltage the overvoltage stress on the
SLIC is minimised.
Overtemperature Protection
A ring lead to ground short circuit fault
condition, as well as other improper
operating modes, may cause excessive
SLIC power dissipation. If junction
temperature increases beyond 160 °C,
the temperature guard will trigger, causing
the SLIC to be set to a high impedance
state. In this high impedance state power
dissipation is reduced and the junction
temperature will return to a safe value.
Once below 140 °C junction temperature
the SLIC is returned back to its normal
operating mode and will remain in that
state assuming the fault condition has
been removed.
Table 1. PBL 3766 operating states
pin to ground. One resistor may be
shared by several SLICs.
Printed Circuit Board Layout
Care in PCB layout is essential for proper
function. The components connecting to
the RSN input should be placed in close
proximity to that pin, such that no
interference is injected into the RSN
terminal. A ground plane surrounding the
RSN pin is advisable. The C_HP capacitor
should be placed close to terminals HPT
and HPR to avoid un-wanted disturb-
ances.
State
number C2 C1
1
00
SLIC
operating state
Open circuit
Active detector
No active detector
DET Output Note 1.
Logic level high
Positive overvoltages are clamped to
2
01
Ringing
Ring trip detector
Ring trip status
ground by an internal diode. Negative
3
10
Active
Loop curr. detector Loop current status
overvoltages are initially clamped close to ₄
11
Stand-by
Loop curr. detector Loop current status
the SLIC negative supply rail voltage. If
sufficient current is available from the
overvoltage, then the protector will crow-
bar into a low voltage on-state condition,
Note
1. E0 = 0, i.e. the DET output is enabled. A logic low level at the DET output
indicates a triggered detector.
clamping the over-voltage close to ground. Table 2. Enable input E0
A gate decoupling capacitor, C_TISP is
Enable
needed to carry enough charge to supply _{state E0}
DET output status
Active detector
a high enough current to quickly turn on
the thyristor in the protector. Without the
capacitor even the low inductance in the
track to the V supply will limit the
Bat
current and delay the activation of the
thyristor clamp.
The fuse resistors R_F serve the dual
purposes of being non-destructive energy
1
0
Active
Loop current or ring trip detector
2
1
High impedance
Note 1.
None
Note 2.
Notes
1. Detector selected according to Table 1.
2. In the high impedance state the DET output appears as a 15 kohms resistor to V_CC
4-17