PBL38650-2 Datasheet, PDF (13/16 Pages) Ericsson – Subscriber Line Interface Circuit

PBL 386 50/2
hook and 1.3 V_Peak on-hook. If a resistor
R_OV is connected between the POV pin
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The R_OV and
corresponding V_TRO (signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
V_TX can not handle more than 3.2 V_Peak. So
if the gain 2-wire to 4-wire is -6.02dB,
6.4 V_Peak is maximum also for the 2-wire
side. Signal levels between 6.4 and
12.8 V_Peak on the 2-wire side can be han-
dled with the PTG shorted so that the gain
G_2-4S become -12.04dB. Please note that
the 2-wire impedance, R_R and the 4-wire to
4-wire gain has to be recalculated if the
PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 29 mA.
How to use POV:
1. Decide what overhead voltage(V_TRO) is
needed. The POV function is only
needed if the overhead voltage exceeds
3.2 V_Peak
2. In figure 11 the corresponding R_OV for
the decided V_TRO can be found.
3. If the overhead voltage exceeds
6.4 V_Peak , the G_2-4S gain has to be
changed to -12.04dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, R_R and
the 4-wire to 4-wire gain has to be
recalculated.
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 50/2 SLIC
reduce the dc line current when the chip
temperature reaches approximately
145°C and increases it again automati-
cally when the temperature drops.
Accordingly transmission is not lost
under high ambient temperature condi-
tions.
The detector output, DET, is forced to a
logic low level when the temperature
guard is active.
K_R
+12 V /+5V
RING
TIP
VB2
VB
D_BB
D_VB
D_VB2
C _VB2
C_VB
R_F2
R_F1
C_GG
OVP
E _RG
R₁
R_RT
R₂
RESISTORS: (Values according to IEC E96 series)
R_SG
R
LD
R_OV
R
LC
R_REF
R_R
R_T
R_TX
R_B
R_RX
R
FB
R₁
R
2
R₃
R₄
R_RT
R_P1, R_P2
R_F1, R_F2
=0Ω
1% 1/10 W
= 49.9 kΩ 1% 1/10 W
= User programmable
= 32.4 kΩ 1% 1/10 W
= 49.9 kΩ 1% 1/10 W
= 11.5 kΩ 1% 1/10 W
= 52.3 kΩ 1% 1/10 W
= 32.4 kΩ 1% 1/10 W
= 57.6 kΩ 1% 1/10 W
= 52.3 kΩ 1% 1/10 W
Depending on CODEC / filter
= 604 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 249 kΩ 1% 1/10 W
= 280 kΩ 1% 1/10 W
= 330 Ω 5% 2 W
≥ 10 Ω
1% 1/10 W (Note 1)
= Line resistor, 40 Ω 1% match
D_HP
R_P2
VB
R_P1
PBL 386 50/2
C_HP
C_RC
C_TC
R_SG
C_LP
PTG
RRLY
HP
NC
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
LP
VTX
AGND
RSN
NC
REF
PLC
POV
PLD
VCC
NC
DET
C1
C _TX
R_T
R_R
R_REF
R _LC
R_OV
R_LD
VCC
R _TX
R_RX
R_B
R _FB
--
0
++
0
CODEC/
Filter
PBL 386 50/2
C _VCC
VCC
DT
C2
DR
C3
C₁
C₂
R₃ R₄
SLIC No. 2 etc.
SYSTEM CONTROL
INTERFACE
CAPACITORS: (Values according to IEC E96 series)
C_VB
C
VB2
C_VCC
C
TC
C_RC
C_HP
C_LP
C_TX
C_GG
C₁
C
2
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
= 150 nF
= 68 nF
= 220 nF
= 330 nF
= 330 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
DIODES:
D_VB
D_VB2
D_BB
DHP
= 1N4448
= 1N4448
= 1N4448
= 1N4448 (Note 2)
OVP:
Secondary protection ( e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
NOTES:
1. R_P1 and R_P2 may be omitted if D_VB is in
place.
2. It is required to connect D_HP between
terminal HP and ground if C_HP >47nF.
Figure 12. Single-channel subscriber line interface with PBL 386 50/2 and combination CODEC/filter.
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