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S1C33L15 Datasheet, PDF (6/6 Pages) Epson Company – CMOS 32-bit Application Specific Controller
„ Block Diagram
S1C33L15
C33PE Core
mi ni Cache
Calculation
M odul e
S1C33L15
Host processor
LCD panel
UDMA
HIF
LCDC
PLL
C MU
ITC
MEMC reg.
UDMA reg.
SIO
(UART/SIF/EFSIO)
SPI
I 2S
TIMER
(T 16/T8)
DCSIO
A3RAM Arbiter
IRAM-2 (64KB)
IRAM-3 (16KB)
DSTRAM (2KB)
CARD
REMC
LCDC reg.
HIF reg.
GPIO
Memory Controller (MEMC)
SD RAMC
SR AM C
MISC
WDT
RT C
RT CVDD
BBRAM Arbiter
BBRAM (2KB)
Boot Sequencer
External memory
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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson.
Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind
arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no
representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license
to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in
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contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan
and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
©Seiko Epson Corporation 2009, All rights reserved.
SEIKO EPSON CORPORATION
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Department
IC International Sales Group
421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814 FAX: +81-42-587-5117
„ EPSON semiconductor website
http://www.epson.jp/device/semicon_e/
Document code: 411214301
First issue Apr, 2008
Revised Dec, 2009 in Japan
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