S1D13700 Datasheet, PDF (55/134 Pages) Epson Company – Embedded Memory Graphics LCD Controller

Epson Research and Development
Vancouver Design Center
Page 55
POWER SAVE
The POWER SAVE command is used to enter standby mode on the S1D13700 when
indirect addressing is used. For further information on the POWER SAVE command, see
Section 11.1.2, “POWER SAVE” on page 73.
REG[08h] Power Save Mode Register
Address = 8008h
Read/Write
n/a
Power Save Mode
Enable
7
6
5
4
3
2
1
0
bit 0
Power Save Mode Enable
This bit controls the state of the software initiated power save mode. When power save
mode is disabled, the S1D13700 is operating normally. When power save mode is
enabled, the S1D13700 is in a power efficient state where all internal operations, including
the oscillator, are stopped. For more information on the condition of the S1D13700 during
Power Save Mode, see Section 17, “Power Save Mode” on page 126.
When this bit = 0, power save mode is disabled (see note).
When this bit = 1, power save mode is enabled (default).
Note
To fully disable power save mode when in Direct mode, a dummy write to any register
must be performed after setting REG[08h] bit 0 = 0. To fully disable power save mode
when in Indirect mode, at least two dummy writes to any register must be performed af-
ter setting REG[08h] bit 0 = 0.
Note
Enabling power save mode automatically clears the Display Enable bit (REG[09h] bit
0). After power save mode is disabled, the Display Enable bit must be set (REG[09h] bit
0 = 1) in order to turn on the display again.
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
S1D13700
X42A-A-001-00