S1D13705 Datasheet, PDF (540/562 Pages) Epson Company – Embedded Memory LCD Controller

Page 12
4 VR4181A to S1D13705 Interface
Epson Research and Development
Vancouver Design Center
4.1 Hardware Description
The NEC VR4181A microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 interface, a glueless interface is achieved. The diagram below shows
a typical implementation of the VR4181A to S1D13705 interface.
NEC VR4181A
S1D13705
#MEMWR
#UBE
#MEMRD
WE0#
WE1#
RD#
#LCDCS
IORDY
Pull-up
CS#
WAIT#
#MEMCS16
A[16:0]
System RESET
D[15:0]
Oscillator
Vcc
Vcc
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
RESET#
AB[15:0]
DB[15:0]
BCLK
BS#
RD/WR#
Figure 4-1: Typical Implementation of VR4181A to S1D13705 Interface
S1D13705
X27A-G-013-02
Interfacing to the NEC VR4181A™ Microprocessor
Issue Date: 01/02/13