S1C63709 Datasheet, PDF (5/6 Pages) Epson Company – 4-bit Single Chip Microcomputer

S1C63709
■ BASIC EXTERNAL CONNECTION DIAGRAM
● When a primary cell is used
LCD panel 64 × 8
Input
K00–K03
K10–K13
K20–K23
K30
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
S1C63709
P13 (SRDY) _{[The potential of the substrate}
I/O
P20 (TOUT)
(back of the chip) is VSS.]
P21 (SVDDT)
P22 (VCWON)
P23 (ISOR1)
P30 (ISOR3)
P31 (ISOR2)
P32 (CLIM)
P33 (F16HZ)
P41 (FOUT)
P40 (BZ)
SLRA
SLRC
VTKP
VDD
RESET
CA
CB
VD1
VOSC
VC1
VC2
VC3
OSC1
OSC2
OSC3
OSC4
TEST
VSS
CRES
+
CP
C1
C2
C3
C4
C5
C6
CGX
X'tal ^∗3
2.1 V ^∗4
|
3.6 V
CGC
CR
CDC
∗1
∗2
M0
M1
X'tal
CGX
CR
CGC
CDC
RCR
C1–C6
CP
CRES
Crystal oscillator
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation
Capacitor
Capacitor
RESET terminal capacitor
32.768 kHz, CI(Max.) = 35 kΩ, CL(Typ.) = 6 pF
0–20 pF
4 MHz (3.0 V)
30 pF
30 pF
75 kΩ (1.1 MHz)
0.2 μF
3.3 μF
0.1 μF
∗1: Ceramic oscillation
∗2: CR oscillation (external R)
∗3: CG regulation
∗4: 1.0–3.6 V when OSC3
is not used or OSC3 CR
oscillation (built-in R)
is used
Note: The above table is simply an example, and is not guaranteed to work.
EPSON
5