SG-710 Datasheet, PDF (1/2 Pages) Epson Company – HIGH-FREQUENCY CRYSTAL OSCILLATOR

Crystal oscillator
HIGH-FREQUENCY CRYSTAL OSCILLATOR
SG-710 series
• Ceramic package with 1.5 mm thickness.
• Excellent shock resistance and environmental capability.
• Low current consumption due to use of C-MOS technology.
• Low current consumption by output enabled function (OE) or
standby function (ST).
Specifications (characteristics)
Item
Output frequency range
Power source
voltage
Temperature
range
Max. supply voltage
Operating voltage
Storage temperature
Operating temperature
Soldering condition
Symbol
SG-710PTK
SG-710PHK
Specifications
SG-710ECK
f0
1.8000 MHz to
50.0000 MHz
1.8000 MHz to
80.0000 MHz
1.8000 MHz to
67.0000 MHz
VDD-GND
-0.5 V to +7.0 V
VDD
5.0 V ±0.5 V
3.3 V ±0.3 V
TSTG
-55 °C to +125 °C
TOPR
-10 °C to +70 °C (-40 °C to +85 °C)
TSOL
Twice at under +260 °C within 10 s
Frequency stability
Current consumption
Output disable current
Standby current
Duty
High output voltage
Low output voltage
Output load
condition (fan out)
TTL
C-MOS
Output enable/disable input voltage
Output rise time
Output fall time
C-MOS level
TTL level
C-MOS level
TTL level
∆f/f0
Iop
IOE
IST
tw/ t
VOH
VOL
N
CL
VIH
VIL
tTLH
tTHL
B: ±50 x 10^-6 C: ± 100 x 10^-6 M: ± 100 x 10^-6
24 mA Max.
12 mA Max.
40 mA Max.
16 mA Max.
18 mA Max.
—
—
45 % to 55 %
2.4 V Min.
0.4 V Max.
10 TTL Max.
(15 pF Max.)
2.0 V Min.
0.8 V Max.
—
5 ns Max.
—
5 ns Max.
—
45 % to 55 %
10 µA Max.
40 % to 60 %
40 % to 60 %
—
VDD -0.5 V Min.
0.5 V Max.
10 TTL Max.
0.9 x VDD Min.
0.1 x VDD Max.
—
50 pF Max.
15 pF Max.
2.0 V Min.
0.7 x VDD Min.
0.8 V Max.
0.3 x VDD Max.
5 ns Max.
6 ns Max.
—
5 ns Max.
6 ns Max.
—
Oscillation start up time
tOSC
10 ms Max.
Aging
fa
±5 x 10^-6/year Max.
Shock resistance
S.R.
±10 x 10^-6 Max.
Remarks
Please contact us on availability of -40 °C to +85 °C
B,C:-10 °C to +70 °C, M:-40 °C to +85 C°
No load condition
OE=GND(PTK, PHK)
ST=GND(ECK)
C-MOS load: 1/2 VDD level
TTL load: 1.4 V level
IOH=-16 mA(PTK,PHK),-2 mA(ECK)
IOL= 16 mA(PTK,PHK), 2 mA(ECK)
_ OE terminal(PTK,PHK)
ST terminal(ECK)
C-MOS load: 10 %→90 % VDD
TTL load: 0.4 V→2.4 V
C-MOS load: 90 %→10 % VDD
TTL load: 2.4 V→0.4 V
Time at minimum operating voltage to be 0 s
Ta= +25 °C, VDD = 5.0 V/3.3 V(ECK)
Three drops on a hard board from 750 mm
or excitation test with 29400 m/s² x 0.3 ms x
1/2sine wave in 3 directions
External dimensions
#4
#3
E 40.000
HC724A
#1
#2
L
5.08
37
Bottom View _1.4
#1
#2
#4
5.08
#3
(Unit: mm)
NO. Pin terminal
1 OE or ST
2 GND
3 OUT
4
VDD
Recommended soldering pattern ^{(Unit: mm)}
1.8
L
W
PTK/PHK/ECK 7.5 Max. 5.0 Max.
∗∗W
7.2 Max. 5.2 Max.
5.08