S1L50000 Datasheet, PDF (1/12 Pages) Epson Company – HIGH DENSITY GATE ARRAY

DATA SHEET
ASIC
S1L50000
S1L50000 SERIES HIGH DENSITY GATE ARRAY
ΠDESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
• Ultra-high-speed, high density and low power consumption
• Low voltage operation: 3.3V and 2.0V
• Number of raw gates: 28,710 ~ 815,468 gates
ΠFEATURES
• Process
0.35µm 2/3/4 layer metalization CMOS process
• Integration
A maximum of 815,468 gates (2 input NAND gate equivalent)
• Operating Speed
• I/F Levels
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
(2-input pair NAND, F/O = 2, Typical wire load)
Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(C_L = 15 pF)
Input/Output TTL/CMOS/LVTTL compatible
• Input Modes
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
• Output Modes
Normal, 3-state, bi-directional, PCI
• Output Drive
• RAM
I_OL = 0.1, 1, 3, 8, 12, 24 mA selectable
(Built-in level shifter is used at 5.0V)
I_OL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
I_OL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
Asynchronous 1-port, asynchronous 2-port
• Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer: Built-in interfaces of both high and low voltages possible
• Operation possible at V_DD = 2.0 ± 0.2V
i i i i EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: [phone] Fax: [phone]
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