S1C63158 Datasheet, PDF (1/2 Pages) Epson Company – 4-bit Single Chip Microcomputer

S1C63158
4-bit Single Chip Microcomputer
● Original Architecture Core CPU
● Low Current Consumption
● Wide-range Operating Voltage (0.9V to 3.6V)
● High Speed Operation in Low Voltage
● A/D Converter
„ DESCRIPTION
The S1C63158 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM
(8,192 words × 13 bits), RAM (512 words × 4 bits), serial interface, watchdog timer, programmable timer, time
base counter (1 system), SVD circuit, a 4-channel A/D converter and a special input port that can implement
key position discrimination function using with the A/D converter. The S1C63158 features low voltage/high
speed (4 MHz Max.) operation and low current consumption (2 μA Typ. in HALT mode), this makes it suitable
for battery driven portable equipment such as a head phone stereo.
„ FEATURES
OSC1 oscillation circuit
OSC3 oscillation circuit
Instruction set
Instruction execution time
ROM capacity
RAM capacity
Input port
Output port
I/O port
Serial interface
Time base counter
Programmable timer
Watchdog timer
A/D converter
Buzzer output
Supply voltage detection (SVD) circuit
External interrupt
Internal interrupt
Power supply voltage
Operating temperature range
Current consumption (Typ.)
Package
32.768 kHz (Typ.) Crystal oscillation circuit or CR oscillation circuit (∗ 1)
2 MHz (Typ.) CR or Ceramic oscillation circuit (∗ 1)
Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
During operation at 32.768 kHz: Min. 61 μsec
During operation at 4 MHz: Min. 0.5 μsec
Code ROM: 8,192 words × 13 bits
Data memory: 512 words × 4 bits
9 bits 8 bits (Pull-up resistors may be supplemented ∗ 1)
1 bit (Input interrupt for key position sensing by A/D)
12 bits (It is possible to switch the 2 bits to special output ∗ 2)
20 bits (It is possible to switch the 4 bits to serial input/output ∗ 2)
(It is possible to switch the 4 bits to A/D input ∗ 2)
1 port (8-bit clock synchronous system)
1 system (Clock timer)
Built-in, 2 channels × 8 bits, with event counter function
or 1 channel × 16 bits (∗ 2)
Built-in
8-bit resolution
Maximum error: ±3 LSB, A/D clock: Max. 1MHz
(0.9 to 3.6 V, VC2 mode should be set when the supply voltage is 1.6 V or less.)
Buzzer frequency: 2 kHz or 4 kHz (∗ 2), 2 Hz interval (∗ 2)
16 values, programmable (1.05 V to 2.60 V)
Input port interrupt: 2 systems
Key sensing interrupt: 1 system
Clock timer interrupt: 4 systems
Programmable timer interrupt: 2 systems
Serial interface interrupt: 1 system
A/D converter: 1 system
0.9 V to 3.6 V
-20°C to 85°C
Single clock:
During HALT (32 kHz) 1.5 V (normal mode) 2 μA
During operation (32 kHz) 1.5 V (normal mode) 4 μA
Twin clock:
During operation (4 MHz) 3.0 V (normal mode) 900 μA
QFP12-48pin, QFP13-64pin (plastic) or chip
∗ 1: Can be selected with mask option
∗ 2: Can be selected with software