EPC660 Datasheet, PDF (1/116 Pages) Espros Photonics corp – 3D TOF Imager 320 x 240 Pixel

DATASHEET – epc660
3D TOF Imager 320 x 240 Pixel
General Description
The epc660 is a fully integrated 3D-TOF imager with a resolution of
320 x 240 pixels (QVGA). It is a highly integrated system-on-chip
camera system. Apart from the actual CCD pixel-field, it includes
the complete control logic to operate the device. Data communica-
tion is done through a high-speed digital 12-bit parallel video inter-
face.
Even for mobile devices, only a few additional components are
needed to integrate 3D camera capability. Depending on the sys-
tem design, a resolution in the millimeter range for measurements
up to 100 meters is feasible. 65 full frame TOF images are deliv-
ered in maximal configuration. By using the advanced operation
modes, this can be boosted up to more than 1000 TOF images per
second! The high degree of integration lays base for straight-for-
ward camera system design with minimal part count. The extreme-
ly high sensitivity of the optical front end allows for a reduced illumi-
nation subsystem and reduces the power consumption of the over-
all system significantly.
An evaluation kit with hard- and software examples and a compre-
hensive manual helps the system designer to speed up system in-
tegration.
Applications
■ People detection and counting
■ Mobile postal parcel size measurement
■ Machine safety
■ Helicopter near terrain flight assistance
■ Car collision avoidance systems
■ Pedestrian detection and breaking systems
■ Man-Machine interface
■ Gesture control
■ Body size measurement
■ General volumetric mapping
Block Diagram
VDDA
VSSA
VDDIO
VSSIO
VDD
VSS
VSEAL
SHUTTER
epc660
RGU
Charge
Pump
13V
EEPROM
SCL
SDA
I²C Slave
JTAG
Pixel
Cont.
&
Seq.
Memory
Memory
Controller
&
Registers
XTALOUT
XTALIN_CLKIN
OSC
PLL
ROW Buffer
ADC Read-Out
320x240
Pixel Field
ADC Read-Out
ROW Buffer
4x Temp.
Sensors
at corners
De-
modulator
TCMI
VDDPXH
VDDPXM
VIR
VFSAB
VSSPX
VBS
VSYNC_PSDIAG_A0
HSYNC_A1
XSYNC_SAT_CFG
DATA[11:1]
DATA0_FS
DCLK
m+n
Clock Delay
Phase
Detector
LEDFB
0
LED2 (push-pull)
1
DLL
LED (open-drain)
CGU
Modulator
LED Driver
VSSLED
Figure 1: Functional Block Diagram
© 2017 ESPROS Photonics Corporation
Characteristics subject to change without notice
1 / 116
Datasheet_epc660-V1.09
www.espros.com