EM484M3244VBE_15 Datasheet, PDF (8/18 Pages) Eorex Corporation – Synchronous DRAM

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AC Operating Test Conditions
(VDD=3.3V0.3V, TA=0°C ~70°C)
Item
Output Reference Level
Output Load
Input Signal Level
Transition Time of Input Signals
Input Reference Level
EM484M3244VBE
Conditions
1.4V/1.4V
See diagram as below
2.4V/0.4V
2ns
1.4V
AC Operating Test Characteristics
(VDD=3.3V0.3V, TA=0°C ~70°C)
Symbol
Parameter
-7.5
Units
Min. Max.
tCK Clock Cycle Time
CL=3 7.5
ns
CL=2 10
tAC Access Time form CLK
CL=3
CL=2
5.4
ns
5.4
tCH CLK High Level Width
2.5
ns
tCL CLK Low Level Width
2.5
ns
tOH Data-out Hold Time
CL=3 2
ns
CL=2 2
tHZ
Data-out High Impedance
Time ^{(Note 5)}
CL=3
CL=2
5.4
ns
5.4
tLZ Data-out Low Impedance Time
0
ns
tIH Input Hold Time
0.8
ns
tIS Input Setup Time
1.5
ns
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to
output voltage levels.
Dec. 2013
www.eorex.com
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