EM47EM3288SBA_15 Datasheet, PDF (32/39 Pages) Eorex Corporation – Double DATA RATE 3 Stack SDRAM

EM47EM3288SBA
Burst Type (A3)
Burst Length ^R/W A2 A1 A0 Sequential Addressing, A3=0 Interleave Addressing, A3=1
4 (chop)
8
R000
R001
R010
R011
R100
R101
R110
R111
W0VV
W1VV
R000
R001
R010
R011
R100
R101
R110
R111
WVVV
0123TTTT
1230TTTT
2301TTTT
3012TTTT
4567TTTT
5674TTTT
6745TTTT
7456TTTT
0123XXXX
4567XXXX
01234567
12305674
23016745
30127456
45670123
56741230
67452301
74563012
01234567
0123TTTT
1032TTTT
2301TTTT
3210TTTT
4567TTTT
5476TTTT
6745TTTT
7654TTTT
0123XXXX
4567XXXX
01234567
10325476
23016745
32107654
45670123
54761032
67452301
76543210
01234567
Note1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock
cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled
in by two clocks. In case of burst length being selected on-the-fly via A12 (/BC), the internal write
operation starts at the same point in time like a burst of 8 write operation. This means that during
on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
Note2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note3. T: Output driver for data and strobes are in high impedance.
Note4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note5. X: Don‟t Care.
Apr. 2014
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