EM47EM0888SBA Datasheet, PDF (31/39 Pages) Eorex Corporation – JEDEC Standard VDD/VDDQ

EM47EM0888SBA
Mode Register Definition
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls
burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various
applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
00
0 PPD
WR
DLL TM
CAS Latency
RBT CL
BL
DLL Control
(for precharge PD)
Slow exit (DLL off)
Fast exit (DLL on)
MRS Mode
MR0
MR1
MR2
MR3
BA1 BA0
0
0
0
1
1
0
1
1
A12
DLL Reset A8
Mode A7
No
0
Normal 0
0
Yes
1
Test
1
1
Read Burst Type A3
Nibble sequential 0
Interleave
1
BL
A1 A0
8
00
4 or 8 (OTF) 0 1
4
10
Reserved 1 1
WR for autoprecharge A11 A10 A9
Reserved
0
0
0
5
0
0
1
6
0
1
0
7
0
1
1
8
1
0
0
10
1
0
1
12
1
1
0
Reserved
1
1
1
CAS Latency A6 A5 A4 A2
Reserved
0
0
0
0
Reserved
0
0
1
0
6
0
1
0
0
7
0
1
1
0
8
1
0
0
0
9
1
0
1
0
10
1
1
0
0
11
1
1
1
0
Note1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.
Note2. WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in
ns) and rounding up to the next integer: WRmin[cycles] = Roundup(t_WR[ns]/t_CK[ns]). The WR value in
the mode register must be programmed to be equal or larger than WRmin. The programmed WR value
is used with t_RP to determine t_DAL.
Apr. 2012
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