EM44DM0888LBA Datasheet, PDF (26/29 Pages) Eorex Corporation – JEDEC Standard VDD/VDDQ

EM44DM0888LBA
Output Drive Strength
The output drive strength is defined by bit A1. Normal drive strength outputs are specified to be SSTL_18.
Programming bit A1 = 0 selects normal (100 %) drive strength for all outputs.
Programming bit A1 = 1 will reduce all outputs to approximately 60 % of the SSTL_18 drive strength.
This option is intended for the support of the lighter load and/or point-to-point environments.
Single-ended and Differential Data Strobe Signals
EMRS
A11
A10
(/RDQS Enable) (/DQS Enable)
0 (Disable)
0 (Enable)
0 (Disable)
1 (Disable)
1 (Enable)
0 (Enable)
Strobe Function Matrix
Signals
RDQS
DM
/RDQS DQS
/DQS
DM
Hi-Z DQS /DQS Differential DQS signal
DM
Hi-Z DQS Hi-Z Single-ended DQS signal
RDQS /RDQS DQS /DQS Differential DQS signal
1 (Enable)
1 (Disable)
RDQS Hi-Z DQS Hi-Z Single-ended DQS signal
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data Qoff bit in the
EMRS(1) is set to (0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM
outputs allows users to measure IDD currents during Read operations, without including the output buffer
current.
Feb. 2012
26/29
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