EM44BM1684LBB_15 Datasheet, PDF (24/28 Pages) Eorex Corporation – Double DATA RATE 2 SDRAM

EM44BM1684LBB
Extended Mode Register Set ( EMRS )
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2 should
be in all bank pre-charge with CKE already prior to writing into the extended mode register. ) The extended
mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of
the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after
power-up for proper operation. The mode register set command cycle time (tMRD) must be satisfied to complete
the write operation to the EMRS(1). Mode register contents can be changed using the same command and
clock cycle requirements during normal operation when all banks are in pre-charge state.
BA2 BA1 BA0 A12
0
0
1 Qoff
A11
RDQS
A10 A9 A8 A7 A6
/DQS _{OCD program Rtt}
A5 A4 A3
Additive latency
A2 A1 A0
Rtt ^D.I.C. DLL
Qoff (Output Buffer) A12
Enabled
0
Disabled
1
RDQS A11
enable
Disable
0
Enable
1
/DQS A10
Enable 0
Disable 1
DLL
A0
Enable 0
Disable 1
OCD Calibration Program
A9
OCD Calibration mode exit
0
Drive (1)
0
Drive (0)
0
Adjust mode (*1)
1
OCD Calibration default (*2)
1
A8 A7
0
0
0
1
1
0
0
0
1
1
*1: When adjust mode is issued, AL from previously set value
setting A9-A7 to 000. Refer to the section Off-Chip Driver (OCD)
MRS Mode
BA1
BA0
must be applied.
MRS
0
0
EMRS(1)
0
1
EMRS(2)
1
0
EMRS(3) Reserved
1
1
*2: After setting to default, OCD mode needs to be exited by
impedance adjustment for detail information
Apr. 2014
24/28
Output Driver
A1
Impedance Control
Normal (100%)
0
Weak (60%)
1
Rtt
ODT Disable
75 ohm
150 ohm
50 ohm
A6 A2
00
01
10
11
Additive Latency
0
1
2
3
4
5
6
Reserved
A5 A4 A3
000
001
010
011
100
101
110
111
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