EM47DM1688SBC_15 Datasheet, PDF (23/38 Pages) Eorex Corporation – Double DATA RATE 3 SDRAM

EM47DM1688SBC
Note 18: Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly, OTF) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly, OTF) : Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.
Note 19: The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the
right side.
Note 20: CKE is allowed to be registered low while operations such as row activation, precharge, auto
precharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those
operation.
Note 21: Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is
satisfied, there are cases where additional time such as tXPDLL(min) is also required.
Note 22: Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
Note 23: One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT
impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output
Driver Voltage and Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application
specific parameters. One method for calculating the interval between ZQCS commands, given the temperature
(Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The
interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
Note 24: The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an
additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to
account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
Note 25: Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the
consecutive crossing of VREF(DC).
Note 26: tDQSL describes the instantaneous differential input low pulse width on DQS - /DQS, as measured
from one falling edge to the next consecutive rising edge.
Note 27: tDQSH describes the instantaneous differential input high pulse width on DQS - /DQS, as measured
from one rising edge to the next consecutive falling edge.
Note 28: tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective
timing parameter in the application.
Note 29: tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective
timing parameter in the application.
Note 30: tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to
the following falling edge.
Note 31: tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to
the following rising edge.
Note 32: n = from 13 cycles to 50 cycles. This row defines 38 parameters.
Feb. 2014
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