EM47FM3288SBB_15 Datasheet, PDF (19/41 Pages) Eorex Corporation – Double DATA RATE 3 Stack SDRAM

EM47FM3288SBB
AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Symbol
t_CK
t_CH, t_{CL (AVG)}
t_RRD
t_FAW
t_IH(base)
DC100
t_IS(base)
AC175
t_IS(base)
AC150
t_DH(base)
t_DS(base)
t_IPW
t_DIPW
t_HZ(DQ)
t_LZ(DQ)
t_HZ(DQS)
t_LZ(DQS)
t_DQSQ
t_CCD
Speed Bin
CL-nRCD-nRP
Parameter
Minmum clock cycle, DLL-off mode
Average CK high/low level width
Active bank A to active bank B
command period (1KB page size)
Four Activate Window
Address and Control input hold time
(VIH/VIL(DC100) levels)
Address and Control input setup time
(VIH/VIL(AC175) levels)
Address and Control input setup time
(VIH/VIL(AC150) levels)
DQ and DM input hold time
(VIH/VIL(DC) levels)
DQ and DM input setup time
(VIH/VIL(AC) levels)
Address and control input pulse width
for each input
DQ and DM input pulse width for
each input
DQ high impedance time
DQ low impedance time
DQS,/DQS high impedance time
RL+BL/2 reference
DQS,/DQS low impedance time
RL-1 reference
DQS,/DQS to DQ skew per group,
per access
/CAS to /CAS command delay
t_QH
DQ output hold time from DQS, /DQS
t_DQSCK
t_DQSS
DQS,/DQS rising edge output access
time from rising CK,/CK
DQS latch rising transitions to
associated clock edges
-125
(DDR3-1600)
11-11-11
Min. Max.
8
-
0.47 0.53
6
-
4
-
30
-
120
-
45
-
45+125 -
45
-
10
-
560
-
360
-
-
225
-450 225
-
225
-450 225
-
100
4
-
0.38
-
-225 225
-0.27 0.27
t_DQSH
DQS input high pulse width
0.45 0.55
-150
(DDR3-1333)
9-9-9
Min.
Max.
8
-
0.47
0.53
6
-
4
-
30
-
Units
ns
ns
ns
nCK
ns
Notes
6
140
-
ps
16
65
-
ps
16
65+125
-
ps 16,24
65
-
ps
17
30
-
ps
17
620
-
ps
25
400
-
-500
-
-
ps
25
250 ps 13,14
250 ps 13,14
250 ps 13,14
-500
250 ps 13,14
-
4
0.38
-255
-0.25
0.45
125 ps 12,13
- nCK
-
t_CK
(avg)
12,13
255 ps 12,13
0.25
0.55
t_CK
(avg)
t_CK
(avg)
27,28
Jul. 2012
19/41
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